Pe Logic Design

8 hours ago

Bengaluru, India Rambus Full time

Overview:
As a **PE Logic Design,** which is a Full-Time position, you will be developing micro-architecture derived from top level architecture specification & design RTL of various digital blocks of the interface IPs, model & lead the top-level integration of macros. You will also develop from different models of complex circuits and integrate them.

**Responsibilities**:

- Help define micro-architecture, design RTL, debug, trace, and be active member of delivering next gen high speed interface physical layer IP’s like DDR5/4/3, HBM3/2E/2, GDDR6, Serdes 28G/32G/56G/64G/112G in advance nodes like 5nm, 7nm, 14nm etc.
- Be responsible for the logic design/ RTL coding and timing closure of multiple blocks in high performance custom integrated circuit environment
- Develop various analog macro models and integrate to enable high coverage, and drive the methodology on mixed signal IP flows on modelling, simulations, and timing closure
- Collaborate with verification team to ensure implementation meets both architectural and micro-architectural intent
- Participate in running quality checks such as Lint, clock domain crossing etc.
- Collaborate with physical design, design for test, co-simulation & timing teams to optimize tradeoffs within the design
- Interact with junior team members & interns and cultivate a growth culture among team to encourage collaboration & inclusion
- Interact and participate in discussion with customer on IP integration and reviews
- Work towards power, performance, and area (PPA) targets or enhancements

Qualifications:

- Master’s degree or bachelor’s degree in Electronics or Electrical Engineering
- 10+ years of relevant work experience in micro-architecture, RTL design, Synthesis, and timing closure
- Substantial background in debugging designs as well as simulation environment
- Driving mixed-signal design flows and improve different methodologies.
- Experience in delivering high-speed, high-performance IP design blocks & integrating them in advanced technology nodes
- Deep understanding of fundamental digital design concepts

**Preferred qualifications**:

- Experience in the design of digital circuits and components in RTL, building/lead the top-level integration as well as in synthesis, timing closure, and power-optimization of digital designs.
- Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python.
- Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc.
- Experience in multi-functional interaction with verification, DFT and physical design teams.
- Understanding of the mixed signal IP flow with modelling and simulation.

**About Rambus**

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

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