Pe Logic Design

14 hours ago

Bengaluru Karnataka, India Rambus Full time

Overview:
**Responsibilities**:
As a “Principal Engineer - Logic Design” in memory interface chip design team, you will
- Develop micro-architecture and RTL design for digital components for DDR memory buffer and other mixed signal chip products.
- Along with logic/RTL design, you will be responsible for synthesis, quality checks (lint, clock domain crossing etc.) and timing closure.
- Develop various analog behavioral models for analog custom blocks to enable high digital verification coverage.
- Collaborate with verification team to ensure implementation meets both architectural and micro-architectural intent.
- Interface with physical design, design for test, co-simulation & timing teams to optimize tradeoffs within the design.
- Drive for power, performance, and area (PPA) targets or enhancements.
- Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion.
- Participate and drive post silicon validation, debug, and customer collaboration.

Qualifications:

- Master’s with 8+ years (or bachelor’s with 10+ years) of experience in micro-architecture, RTL design, Synthesis, and timing closure for designs using multiple clock domains.
- Experience coding within Verilog and/or System Verilog along with scripting languages such as Shell, Tcl, or Python.
- Experience with low power design techniques and methodologies
- Knowledge of high-speed chip to chip interfaces (memory PHY, SerDes) is a strong plus.
- Experience in mixed signal designs is preferred.

**About Rambus**

Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.

Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.

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