Asic Digital Design Engr, Ii

2 days ago

Bengaluru, India Synopsys Full time

43618BR
- INDIA - Bangalore

**Job Description and Requirements**
- BS/MS in EE/EC with 3+ years of relevant experience in the design of IP cores and/or SOC
- Must have proven experience in Verilog, System Verilog, assertion coding, and design and synthesis tools usage.
- Experience on memory interface protocols (DDR, LPDDR) is highly desirable.
- Good communication skills, debug and problem solving skills and should be self motivated

Preferred Experience
- Be a technical contributor in the Design Tasks - System Verilog, Verilog coding of RTL modules, State machines, assertions, synthesize the design,,etc.
- Creates deliverables which do not require close review or supervision by a Senior Technical Engineer
- Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
- Familiarity with HVLs such as System Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable.
- Works in a project and team oriented environment with teams spread across multiple sites, worldwide. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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