Asic Digital Design Engr, Ii

2 weeks ago

Bengaluru, India Synopsys Full time

**Job Responsibilities -**
- Work on Architecture, RTL Design and own VESA VDC-M-1.1/1.2 Video Codec products targeted towards AR/VR, MIPI DSI, HDMI 2.1 and DisplayPort Protocols
- Comprehend Standard Specifications and functional specifications
- Create architecture and micro-architecture
- Be an individual contributor handling Micro Architecture Design, Propose options for PPA trade off
- Verilog/System Verilog RTL coding, LINT
- Functional Verification and debug of failures and RTL fixes
- CDC, RDC and STA analysis

**Must have BSEE in EE with 4+ years of relevant experience or MSEE with 3+ years of relevant experience in the following areas**:

- Hands on experience in design of data path designs and algorithmic blocks like VESA DSC-1.1/1.2 video codecs, H.263/H.264 Video codecs, Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj,ck,bs specifications, BCH codes, Parallel CRC computation architectures, MAC SEC engines.
- Hands-on experience in translating the algorithm specification given in C/C++ to Micro architecture and RTL Design for area, latency, throughput trade-offs
- Knowledge of one or more of protocols/standards: VESA VDC-M, DSC, HDMI 2.1, MIPI DSI, AMBA (AXI,APB,AHB)
- Experience with control path-oriented designs like asynchronous FIFOs, SPRAM/ DPRAM interface design, and designs with multiple clocks involving various Clock Domain Crossing schemes.
- Experience with Perforce or similar revision control environment
- Knowledge of Perl/Shell scripts.
- Exposure to quality processes in the context of IP design and verification is an added advantage
- Good communication skills, a team player with good problem solving skills and show high levels of initiative.

**This position requires prior industry experience and is not open for college fresh grads.**

**Location: Bangalore**

**Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.**

**Country**:

- ** India**

**Job Subcategory**: ASIC Digital Design
- **Job Category**: Engineering

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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