Internship Vlsi

5 days ago


Bengaluru, India MAXVY Full time

Location : Bangalore

Experience : 1 Year

Education : B.E, M.Tech, B.Tech

Role:
Should have knowledge in SystemVerilog, Verilog, UVM

Should have knowledge in Testbench Architecture, Verification Plan

Knowledge Protocol AHB/APB, I2C

Python and Perl script knowledge

must be available to work from office

Job Description:
Testcase running and testplan development

Run regression and coverage analysis.

Work with RTL Team

Salary : 10K


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