Sta, Synthesis

4+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging...

Location Bengaluru - Experience Range 3 - 5 Years Job profile needs Synthesis, STA & FV knowledge. PNR & STA knowledge as well will be considered.

Desired Exp: 5 to 8 YearsJD:Timing analysis, validation and debug across multiple PVT conditions using Tempus.Familiar with Tempus DMMMC flow for STASTA setup, convergence, reviews, and signoff for scan and func.Review of Unconstrained endpoints and check timing reports.Proficient in STA and timing methodologies with good understanding of noise, crosstalk,...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

Job OpportunityWe are seeking a highly skilled Senior STA Specialist to lead our static timing analysis team. The ideal candidate will have expertise in developing and implementing STA methodologies and tools to ensure timely delivery of complex IC designs.Leverage your knowledge of prime-time constraint development to drive full-chip level optimization and...

Job Description- Timing analysis, validation and debug across multiple PVT conditions using Tempus.- Familiar with Tempus DMMMC flow for STA- STA setup, convergence, reviews, and signoff for scan and func.- Review of Unconstrained endpoints and check timing reports.- Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...