
System Design
4 days ago
Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.
We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.
As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.
The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:
**Accountability**
Defines efficient technical solution (QCD) for each gap, promoting a generic approach with a “Kill gap” mindset, and organizing internal Design Reviews with Métier stakeholders;**Main Task**:
- Identifies compliancy gaps between customer requirements and reference platform baselines;
- Gathers gap quotations at tender stage, recording related evidences from all development stakeholders;
- Consolidates gaps QCD at project stage with program System Engineering Manager / Program Manager for baseline "Scope freeze” milestones and with regular updates of platform gap costing file;
- Provides technical support to project team to anticipate deployment issues and to help project stick to a simple solution of good quality following standard deployment processes defined by platform;
- Monitors that project stays in line with platform roadmap and delivery plan, keeping program System Engineering Manager / Program Manager in the loop for all decisions and meetings that may impact on program baselines.
**Education Type**
- Associate Degree-Electronics and Instrumentation Engineering
**Job Type**
- Full Time-Regular
**Experience Level**
- Mid Level
**Total Years of Exp**
- 6 - 9
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Verification Lead Design Engineer
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RTL Release Principal Design Engineer
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Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...
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RTL Release Principal Design Engineer
7 days ago
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Verification Lead Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. 5+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs...
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Verification Lead Design Engineer
5 days ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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Verification Lead Design Engineer
3 days ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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RTL Release Principal Design Engineer
3 weeks ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
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RTL Release Principal Design Engineer
2 days ago
Bengaluru, Karnataka, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
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Sr Principal RTL Design Engineer
7 days ago
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