Design Verification

Key Responsibilities: - Develop and execute verification test plans based on design specifications. - Create constrained-random and directed testbenches using SystemVerilog/UVM. - Develop functional coverage models and drive coverage closure. - Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. - Perform block-level...

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or...

Key Responsibilities:Develop and execute verification test plans based on design specifications.Create constrained-random and directed testbenches using SystemVerilog/UVM.Develop functional coverage models and drive coverage closure.Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.Perform block-level and/or...

Key Responsibilities:Develop and execute verification test plans based on design specifications.Create constrained-random and directed testbenches using SystemVerilog/UVM.Develop functional coverage models and drive coverage closure.Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.Perform block-level and/or...

Key Responsibilities:Develop and execute verification test plans based on design specifications.Create constrained-random and directed testbenches using SystemVerilog/UVM.Develop functional coverage models and drive coverage closure.Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.Perform block-level and/or...

Key Responsibilities:Develop and execute verification test plans based on design specifications.Create constrained-random and directed testbenches using SystemVerilog/UVM.Develop functional coverage models and drive coverage closure.Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.Perform block-level and/or...

Key Responsibilities:Develop and execute verification test plans based on design specifications.Create constrained-random and directed testbenches using SystemVerilog/UVM.Develop functional coverage models and drive coverage closure.Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.Perform block-level and/or...

We are hiring for Design Verification role to join our HCLTech family in Kochi.MDA - Custom Layout (1.) To design Soft core and fabrication (2.) To develop code and do Code Synthesis| place & Route (3.) To identify Target Technology and define Micro Architecture (4.) To procure and manage vendor (5.) To select suitable device/hardware for the assigned module...

We are hiring for Design Verification role to join our HCLTech family in Kochi. MDA - Custom Layout (1.) To design Soft core and fabrication (2.) To develop code and do Code Synthesis| place & Route (3.) To identify Target Technology and define Micro Architecture (4.) To procure and manage vendor (5.) To select suitable device/hardware for the assigned...

6+ years of hands-on DV experience in System Verilog/UVM.Must be able to own and drive the verification of a block / subsystem or a SOC.Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM