Intern

2 weeks ago

Hyderabad Telangana, India Synopsys Full time

We are looking for an Intern (Technical Engineering) to join a growing, dynamic, and multi-cultural engineering team at the heart of a worldwide semiconductor CAD community. If your passion is to work in a challenging environment with a tremendous learning & growth potential, you can become one of us. Capable of understanding requirements and come up with creative solutions, following existing procedures but have a critical perspective regarding what they are doing and can tradeoff the optimal with the best on a daily basis.

**Primary Responsibilities Include**:

- Design, develop, troubleshoot or debug IC physical verification tools, runsets and flows for the development of integrated circuits.
- Development and support of Design Rule Check (DRC), Layout Versus Schematic (LVS), FILL runsets for advanced processes.
- Understanding of complex layout design rules and layout of complex semiconductor devices.
- Creation and execution of QA test cases and regression suites including both schematic and layout entry.
- Support a global layout design team by debug flow, tool, runset and layout issues.
- Develop routines and utility programs to aid in verification of layout design.
- Build productive working relationships with cross functional teams.

**Key Qualifications**:

- BS or MS degree in Electronics & Communication Engineering or similar.
- Good programming skills in at least one or more languages like TCL, Python, Perl, bash
- Familiarity with physical verification flows like LVS/DRC/PEX would be preferred.
- Background knowledge of circuit theory would be an advantage
- Experience with UNIX/Linux environment
- Capability to produce adequate technical documentation
- Exceptional desire to learn, explore new technologies and demonstrate good investigation and problem-solving skills
- Good communication skills

Key words: Layout, Physical Verification, Runset, LVS, DRC, ICV, ICVWB, Python, Tcl

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