Asic Digital Design Engr, Ii

4 days ago

Bengaluru, India Synopsys Full time

41300BR
- INDIA - Bangalore

**Job Description and Requirements**
- Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and review and meeting quality metric goals and regression management.-
**Key Qualification**
- BS/MS in EE/EC with 4+ years of relevant experience in the verification of IP cores and/or SOC
- Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
- Experience on memory interface protocols (DDR, LPDDR) is highly desirable.
- Exposure to IP design and verification processes including VIP development is an added advantage.
- Good communication skills, debug and problem solving skills and should be self motivated

**Preferred Experience**
- Be a technical contributor in the Verification Tasks - System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, Formal verification etc.
- Creates deliverables which do not require close review or supervision by a Senior Technical Engineer
- Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
- Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable
- Works in a project and team oriented environment with teams spread across multiple sites, worldwide

**Job Category**
- Engineering

**Country**
- India

**Job Subcategory**
- ASIC Digital Design

**Hire Type**
- Employee

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