Asic Digital Design Engr, Ii
6 days ago
Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and analysis and meeting quality metric goals and regression management.**Requirements**:
- BS in EE with atleast 3 years of relevant experience or MS with 1+ years of relevant experience in the verification of IP cores and/or SOC RTL designs.
- Must have experience in developing HVL (System Verilog) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
- Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
- Expertise on verification methodologies such as VMM/OVM/UVM/ is required.
- Working knowledge and experience of one or more of the connectivity protocols such as MIPI UFS/Unipro,I3C and AMBA is preferred.
- Familiarity with HDLs such as Verilog and scripting languages such as Perl is highly desired.
- Exposure to IP design and verification processes including VIP development is an added advantage.
- There will be strong focus on functional coverage driven methodology. So the corresponding mindset is a must.
- It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven.
**Job Category**
- Engineering
**Country**
- India
**Job Subcategory**
- ASIC Digital Design
**Hire Type**
- Employee
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