Senior STA Engineer
2 weeks ago
- Senior STA/Synthesis Engineer (Timing Constraint Manager product)
- Location: Bangalore
- Experience: 4yrs to 8yrs
- Bachelor/Master in EE/CS with 4 years of relevant experience
- Proficiency with STA, and SDC.
- Proficiency with RTL and System Verilog.
- Strong Perl, Tcl, or Python scripting skills.
- Strong understanding of front-end EDA design methodologies.
- Prior experience with logic synthesis tools is required.
- Prior experience using or supporting SDC tools would be a significant plus.
- Prior experience with RTL simulation, SVA would be a plus.
- Prior experience supporting front-end EDA tools would be a plus.
- Responsibilities include working with customers to ensure that our SDC Constraints solution meets their expectations; and working on design methodologies that integrate our SDC constraints solution with other Synopsys products.
- You will track customer engagements, and communicate status with Marketing and Upper Management. You will prepare and deliver technical presentations to customers, and FAEs. You will develop customer training material related to our SDC Constraints solution. You will routinely meet with customers and communicate their key priorities internally. You will provide technical direction to our R&D team, and champion and prioritize key customer requests.
Please share your updated CV with or refer those who would like to explore this opportunity.
- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.
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