Senior manager
1 month ago
Job Description The position involves design verification of next generation IP’s with emphasis on verifying and signing off performance and power along with functionality.
This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques.
Candidate will require close interactions with Design, So C , Validation, Synthesis & PD teams for design convergence.
Candidate must be able to take ownership of IP/Block/SS verification.
We are looking for a strong DV manager for Silicon Labs Digital Verification group , 15-20 years’ experience in working in and managing/leading world class execution teams for complex IP verification (UVM, formals, HW/SW, low power, gate level simulations etc.
are few things we are looking for), with some exposure to analog mixed signal verification (IOs, Serdes, PHYs, PLLs etc.) an added plus.
This is an opportunity to work with and be part of world class IP design and verification global teams within Silicon Labs, take part in design and development for building IP's for Silabs SOCs, as part of our future roadmap.
Responsibilities: Develop and track execution of IP level test planning to meet product requirements and established quality standards.
Lead a team to complete the pre-silicon verification of all IP’s Communicate test progress, test results, and other relevant information to project lead Develop or update tests to satisfy the test plan requirements.
Tests will be combination of directed (C tests), constrained random (UVM), and formal verification.
Experience in all So C bus protocols (APB, AXI, AMBA), NVMe or UFS, Ethernet or AXI or DDR protocols Coordinate verification activities with a global team and the design lead.
Provide succinct weekly status and drive action items to closure.
Oversee, direct & engage in the Central IP ’s verification programs from definition through final release, including: Component, System & So C verification projects Requirements management with stakeholders Architecture definition and planning Verification environment development Execution/Debug (e.g., directed testcases, constrained random, assertions, Formal, gate-level) Closure, including review & sign-off on all coverage metrics Train / mentor /guide junior Verification team members Communicate effectively and efficiently to the team, upper management, and stakeholders Be responsible for a verification’s project schedule, scope, cost, and success Leading and inspiring cross-functional and virtual teams to achieve program’s objectives Drive solutions to problems encountered to minimize impact to both cost and schedule Expert knowledge of System Verilog Expert knowledge and experience with an Industry verification methodology UVM Data gathering and analysis to understand gaps and issues in processes and tools Highly proficient with logic simulators (i.e., Xcelium, Questa), debuggers (i.e., Verdi) and issues tracking tools (i.e., JIRA) Experience with requirements & verification management tools (e.g., JAMA, v Manager, VIQ) a plus Experience Level: 12-20 years in Industry Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage.
Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Analytical debugging skills Verify and debug low-power design Mixed Signal Real Number Modeling (RNM, Spice) Analyse formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws Code and functional coverage objects of different blocks Preferred Qualifications: Manage a team of ~10 verification engineers to perform the above tasks Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Working proficiency in MS Project, Excel, Power Point, One Note, Linux environment, scripting languages (e.g., Python, TCL, Perl) and data management version control systems a plus Automating processes and structures to reduce repetitive tasks Skills Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support
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