Sr verification principal design engineer

This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...

Eximietas Design Hiring Senior Design Verification Architects/ Sr. Manger. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: # Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. # Develop and...

Eximietas Design Hiring Senior Design Verification Architects/ Sr. Manger.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:# Lead SoC Design Verification efforts for complex projects, ensuringsuccessful execution of verification plans.# Develop and...

Eximietas Design Hiring Senior Design Verification Architects/ Sr. Manger. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1 B or Already in US. Job Description: # Lead So C Design Verification efforts for complex projects, ensuring successful execution of verification plans. # ...

12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o...

12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/e RM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or...

12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o...

Design Verification Engineer - Senior / Lead / Sr. Lead Job Description: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in Verilog, System Verilog or System C Experience of working on Functional Verification, So C Verification, Emulation...

Design Verification Engineer - Senior / Lead / Sr. Lead Job Description: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good...

Design Verification Engineer - Senior / Lead / Sr. Lead Job Description: Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.. Experience of working in complex test-bench/model in Verilog, System Verilog or System C Experience of working on Functional Verification, So C Verification,...