Dft design- staff
4 days ago
Please Note: This position is not suitable for software testers. Kindly refrain from applying.
Location: Noida (Hybrid – 3 Days Work from Office)
Experience: 7 to 15 years
We are looking for a technical leader to drive the DFT aspects of high-performance compute SOC/MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs.
Key Responsibilities:
Hierarchical scan insertion and SSN-based ATPG flow
MBIST integration & verification at RTL level
LBIST RTL integration, verification, and GLS enablement
Implementation & verification of IEEE JTAG, IJTAG
Post-silicon debug for DFT patterns
Close collaboration with RTL, PD, and Verification teams
Mandatory Skills:
Expertise in Tessent
Proficiency in scripting languages (TCL, Perl, or Python)
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