Tech Lead, VLSI Design
2 days ago
Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.
InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.
Job Description
As Technical Lead - VLSI Design, you will be the key contributor of ORAN SoC product development in the design team and collaborate with FW & design team for product requirement definition, micro architecture study. You will participate in the implementation & verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. Beyond the technical contribution, you will also interface with functional leads in project coordination for schedule tracking on deliverables and dependencies. You also will provide technical advice to young engineers to ensure the quality of work. This role is an excellent opportunity for engineers with 10+ years of industrial experience to grow their technical career as well as leadership to climb up corporate ladders and join the exciting cellular product market space.
Key Responsibilities:
Participate in SoC specifications reviews and contribute to micro-architecture definitions.
Front end digital design and implementation – RTL Coding, Lint, CDC, and Synthesis.
Develop design constraints and coordinate to debug both functional and DFT test issues. • Supervise/mentor young engineers for task assignment and ensure productivity and quality. • Project coordination and status update.
Debug designs, provide timely closure and help to improve SoC design methodologies and verification quality.
Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for timely closure of assigned blocks design and implementation issues.
Job Requirements :
Master’s and/or Bachelor’s Degree in Engineering (or equivalent) in EC/ EE/ CS with 10 or more years of experience in digital SoC development.
Experience in RTL design using Verilog/VHDL and System Verilog for CPU/control sub-systems (AXI/AHB/APB bus, PCIe, PIPE interface), digital signal processing blocks (FIR filter, FFT/IFFT, NCO) & Analog Serdes block.
Experience of front-end tools (Verilog simulators, linters, clock-domain-crossing checkers)
Experience in Gate Level Simulation (GLS) and LEC checking.
Good understanding on back-end design flow on logic synthesis, constraints, timing analysis, DFT etc.
Proven knowledge of System Verilog assertions, checkers, and other design verification techniques.
Knowledge of languages such as C/C++, Perl, Tcl and Python.
Good verbal and written communication and presentation skills.
Team player with ability to collaborate with cross-functional teams to resolve issues effectively. Desirable Skills:
RTL coding & simulation (Verilog/System Verilog/VHDL), Lint, CDC, and Synthesis.
Experience in Cadence front end tools: Xcelium, SimVision, Jasper RTL Apps
Python, Perl scripting for verification automation and report generations.
MS Office tools: Excel, power point, Word doc, Visio etc.
Able to work effectively with incomplete or changing requirements.
Benefits:
Competitive salary and stock options.
Learning and development opportunities.
Employer paid health Insurance.
Earned, Casual, Sick & parental leaves
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