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  • bangalore, India LeadSoc Technologies Pvt Ltd Full time

    📢 Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you!LeadSoc Technologies is hiring for STA Professionals!Exp- 3 yrs to 6 yearsLocation: Bangalore* Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at*...


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    Key Responsibilities:  Develop, support, and optimize STA CAD flows and methodologies using Synopsys PrimeTime for VLSI designs.  Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.  Develop scripts and automation solutions using TCL, Perl, and Python for timing analysis, report generation,...

Static timing analysis engineer

1 month ago


Bangalore, India LeadSoc Technologies Pvt Ltd Full time

So C level – Static timing Analysis Engineer Experience : 10+ years of relevant experience Expectations: Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations independently on So C level. Experience in handling STA of multi-power domain designs. STA flow enhancement, abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Proficient with EDA tools from Synopsys/Cadence. Excellent analytical & communication skills. Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Please share your profile to for further discussion