Static timing Analysis Engineer

📢 Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you!LeadSoc Technologies is hiring for STA Professionals!Exp- 3 yrs to 6 yearsLocation: Bangalore* Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at*...

SoC level – Static timing Analysis EngineerExperience : 10+ years of relevant experienceExpectations:Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on SoC level.Experience in handling STA of multi-power domain designs.STA flow enhancement, abstraction with bottleneck...

SoC level – Static timing Analysis Engineer Experience : 10+ years of relevant experience Expectations: Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations independently on SoC level. Experience in handling STA of multi-power domain designs. STA flow enhancement, abstraction with bottleneck...

Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you! Lead Soc Technologies is hiring for STA Professionals! Exp- 3 yrs to 6 years Location: Bangalore * Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO...

Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you! LeadSoc Technologies is hiring for STA Professionals! Exp- 3 yrs to 6 years Location: Bangalore * Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO...

Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you! LeadSoc Technologies is hiring for STA Professionals! Exp- 3 yrs to 6 years Location: Bangalore * Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO...

Company : a leading Product Engineering company specializing in Semiconductor, Embedded, Artificial Intelligence, and Automotive domains.Location : Bangalore, HyderabadEmployment : Full Time. Permanent on-roll job with the companyNotice Period : Immediate to 90 days noticeExperience : 3 to 12 yearsJob Description : - Perform static timing analysis on...

Key Responsibilities:  Develop, support, and optimize STA CAD flows and methodologies using Synopsys Prime Time for VLSI designs.  Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.  Develop scripts and automation solutions using TCL, Perl, and Python for timing analysis, report...

Senior STA & ECO Engineer (Test & Validation, Staff Engineer) Experience : 4yrs to 10 years Location: Bangalore Job Description: We are looking for Test & Validation, Staff Engineer to join the design intent testing team for STA & ECO . This is an exciting opportunity to be part of product validation team to qualify tools with customer flows across the...

Senior STA & ECO Engineer (Test & Validation, Staff Engineer)Experience : 4yrs to 10 yearsLocation: BangaloreJob Description:We are looking for Test & Validation, Staff Engineer to join the design intent testing team for STA & ECO .This is an exciting opportunity to be part of product validation team to qualify tools with customer flows across the...

Senior STA & ECO Engineer (Test & Validation, Staff Engineer)Experience : 4yrs to 10 yearsLocation: BangaloreJob Description:We are looking for Test & Validation, Staff Engineer to join the design intent testing team for STA & ECO .This is an exciting opportunity to be part of product validation team to qualify tools with customer flows across the...

Key Responsibilities:  Develop, support, and optimize STA CAD flows and methodologies using Synopsys PrimeTime for VLSI designs.  Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.  Develop scripts and automation solutions using TCL, Perl, and Python for timing analysis, report...

Senior STA & ECO Engineer (Test & Validation, Staff Engineer)Experience : 4yrs to 10 yearsLocation: BangaloreJob Description:We are looking for Test & Validation, Staff Engineer to join the design intent testing team for STA & ECO.This is an exciting opportunity to be part of product validation team to qualify tools with customer flows across the technology,...

Senior STA & ECO Engineer (Test & Validation, Staff Engineer) Experience : 4yrs to 10 years Location: Bangalore Job Description: We are looking for Test & Validation, Staff Engineer to join the design intent testing team for STA & ECO . This is an exciting opportunity to be part of product validation team to qualify tools with customer flows across the...

Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you!LeadSoc Technologies is hiring for STA Professionals!Exp- 3 yrs to 6 yearsLocation: Bangalore* Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at* Top...

📢 Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you!LeadSoc Technologies is hiring for STA Professionals!Exp- 3 yrs to 6 yearsLocation: Bangalore* Proven experience in constraints (Func/Test) handling, block and top level static timing analysis, ECO generation at*...

Key Responsibilities: Develop, support, and optimize STA CAD flows and methodologies using SynopsysPrimeTime for VLSI designs. Collaborate with design and implementation teams to establish timing constraints andensure timing closure. Develop scripts and automation solutions using TCL, Perl, and Python for timinganalysis, report generation, and...

Key Responsibilities: Develop, support, and optimize STA CAD flows and methodologies using SynopsysPrimeTime for VLSI designs. Collaborate with design and implementation teams to establish timing constraints andensure timing closure. Develop scripts and automation solutions using TCL, Perl, and Python for timinganalysis, report generation, and...

Key Responsibilities:  Develop, support, and optimize STA CAD flows and methodologies using Synopsys PrimeTime for VLSI designs.  Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.  Develop scripts and automation solutions using TCL, Perl, and Python for timing analysis, report generation,...

Advance your career with Leadsoc Technologies !Experience : 8+ years of relevant experienceExpectations:Candidate should have strong STA fundamentals.Has done timing sign-off including timing margin calculations independently on SoC level.Experience in handling STA of multi-power domain designs.STA flow enhancement, abstraction with bottleneck...