Soc verification engineer
4 weeks ago
• You will be responsible for driving verification strategy, writing Test Plan, developing/modifying Test Bench.
• Working on So C DV signoff using C and/or SV-UVM.
• Reuse of IP DV UVM components like agent, driver, monitor and score board at So C.
• Define and meet all structural and functional coverage goals
• So C verification in RTL, GLS & AMS.
• Actively collaborate with IP/Architecture and RTL teams to enable meeting Verification goals for the So C
Qualifications :
• 1-2 Years’ experience working on So C/IP DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations
Skills:
• Experience in one or many of the following : UVM/System Verilog/C/C++/scripting, Simulation, Formal verification, or post Silicon validation
• Thorough knowledge of standard protocols. Ex: AHB, APB, CAN, Ethernet, USB, I2 C, SPI, UART etc
• Work experience on C based environment with complex ARM processor based systems is a big plus
• Strong in digital design fundamentals, computer organization & architectures and bus protocols
• Excellent debugging and problem solving skill
• Experience with Cadence tools (IUS/Xcelium)
• Exposure to AMS and/or multicore So C DV is a plus.
• Effective communication skills to interact with all stakeholders.
• Must be highly focused and remain committed to obtaining closure on project goals
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