Rtl design lead

3 months ago


Bangalore, India Texas Instruments Full time

The Sitara MPU product line is a rapidly expanding business within TI, investing to address the fast-growing segment of high-performance processors in industrial & automotive markets This product line will enable a scalable portfolio of ARM based high-end MPUs as emerging trends in AI & analytics, motor control, robotics, HMI and real-time networking are shaping the evolving requirements for applications like autonomous robots, renewable energy, factory and home automation.

The newly formed Sitara MPU team in India will focus on expanding the breadth of TI’s portfolio by scaling the execution of MPU devices in 16 FF node and is looking for passionate leaders who can partner to make this a reality Responsibilities : Lead a So C FE team to own So C integration of a complex ARM architecture based So C upto RTM Manage a high impact FE team and take accountability for their timely deliverables Interact and engage early-on with So C system architect and ensure performance analysis, functional safety requirements, system level use-cases and pin mixing is fully comprehended Drive complete So C integration, LEC, LINT checks and CDC/RDC analysis to ensure high quality deliverables Responsible for ensuring power intent of the So C is understood and implemented correctly through Low-Power checks like CLP Ownership of power estimation through the cycle and responsible for meeting/beating active and leakage power targets for the device in different modes Collaborate with systems, IP and DV teams to align on feature updates, bug fixes, IP deliverables and ensure timely So C integration releases that cater to Product Requirements Qualifications : Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 8 to 12 years of experience in IP/So C/subsystem design/integration Skills : Experience with integration of So C’s with ARM processors, complex bus architectures Well experienced with analysis and understanding of system level use case scenarios, safety requirements etc Experience with So C power analysis and power optimization through innovative schemes · Strong experience with advanced low power techniques and tools such as UPF/CPF, CLP Good understanding of constraints development for Physical Design implementation / Static Timing Analysis Experience with industry standard Front End tools like Jasper Gold, Spy Glass, LEC etc Well experienced with EDA tools such as VCS/Questa/Incisive simulators, Debug tools and Formal verification tools Good understanding of So C Debug architectures, Design-for-Debug, Design-for-Test will be highly desirable.

Strong written and verbal communication skill with the ability to explain and present complex ideas Passionate about mentoring and developing people in their careers


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