Rtl design lead
1 month ago
IP RTL Design Lead Who are we and what do we do? Part of the Embedded Processors group of TI, the Processors and Application Specific Microcontroller (ASM) Business Units develop cutting edge system-on-chips (So Cs) for broad microcontrollers and processors spanning even 5nm technologies for applications in industrial and automotive spaces.
The team has been responsible for architecting and developing differentiated IPs with several patented technologies that deliver the best-in-class ADAS, Zonal, Domain controller, Real-Time Control application performance in the market.
The team’s charter includes design of high-performance CPU cores, math co-processors, high performance interconnects, networking and multimedia controllers, safety and security infrastructure, application-tuned control and communication peripherals to enable competitive product creation for our businesses under Embedded Processors.
What will you be doing in this role? (Responsibilities) Micro-architecture development and implementation of IPs working closely with Systems and Architecture teams.
Leading a team of RTL engineers to planning and executing high quality IP development.
Quality checks of the implemented RTL with LINT, CDC and DFT rules, and clear documentation of exceptions and waivers.
Synthesis and timing closure of implemented IP along with equivalence checks.
Provide quality documentation of IP implementation and other deliverables with systematic reviews.
Work closely with IP and So C verification teams to achieve high quality IP delivery.
Provide support to So C Integration, constraint development and timing closure.
Contribute and drive quality/cycle time improvement methodologies as a part of the development process.
Be a team player working across functional teams responsible for development of IP/So Cs from spec to silicon.
What do we expect from you? (Mini Qualifications) Strong RTL design experience of 10+ years with IP designs for microcontrollers expected.
Design experience with high performance Bus Architectures, high speed communication interfaces, Analog Mixed Signal IPs is required.
Strong mentoring and team building skills to lead the team to high performance.
Experience with any of the Hardware Accelerators for mathematical functions, control peripheral designs, networking, multimedia interfaces around display, video and graphics will be a plus.
Must have strong multi-clock domain design knowledge and expertise in Clock Domain Crossing (CDC) analysis tools.
Experience in RTL synthesis, optimization for power and timing are critical needs.
Experience with scripting and automation including IPXACT exposure would be a bonus.
If the idea of correct-by-construct design and efficiency improvement methodologies drives you, we have the best place for you.
Preferred Skills/ Experience Must have 10+ years of experience in hands-on IP development and leading teams.
Strong experience in Micro-architecting, RTL implementation, CDC, Synthesis, Equivalence check and timing checker tools are required.
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