Principal low power verification engineer
1 month ago
Principal /Senior Staff / Staff - Low Power Verification: 1 Position
So C Verification +
Experience in defining and verifying Low power sequences at So C level including clock and power gating
Experience in different low power boot, sleep and recovery modes
6-12 years of experience in working on So C verification environments.
Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and So C.
Experience in CPU(preferably ARM) based verification, C/C++ and/or hardware verification languages e.g. (System Verilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Exposure to all stages of verification requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support.
Experience in verification of So C Debug components - DAP, Trace, ELA etc
Experienced in one or many of these technologies/ protocols – DDR, HBM, PCIe, CXL, Ethernet, Coherent Interconnects and RAS.
System understanding of IOMMU and Interrupt Controllers.
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers.
Contact:
Uday
Mulya Technologies
" Mining The Knowledge Community"
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