Digital Verification Engineer with Low-Power Expertise
5 days ago
We are seeking an experienced Digital Verification Engineer to join our team at Silicon Labs. As a key member of our verification team, you will be responsible for developing and executing testbenches and verification environments for complex digital designs.
About the RoleThe ideal candidate will have 6-8 years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS). You will work closely with cross-functional teams to define and execute gate-level simulation test plans, develop and implement gate-level simulation strategies for complex digital designs, and conduct gate-level simulations to verify the functionality and performance of digital designs.
Responsibilities- Develop and execute comprehensive test plans for gate-level simulations.
- Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues.
- Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations.
- Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations.
- Verify and debug low-power design
- Debug SDF Back Annotated Gate Simulations
- Familiarity with static timing analysis (STA) and power analysis.
- Understanding of power domains and HW programming guide sequences
- Develop test plan to verify all low power states
- Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals
- 6+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS).
- Proven experience in developing and executing testbenches and verification environments.
- Strong skills in performing gate-level simulations and analyzing results.
- Verify and debug low-power design
- Debug SDF Back Annotated Gate Simulations
- Low-power implementation (UPF)
- Mixed Signal Real Number Modeling (RNM, Spice)
- Strong System Verilog/UVM based verification skills
- Experience with Assertion coverage-based verification methodology
- Experience in formal / static verification methodologies will be a plus
- Good understanding of low power design techniques
- Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
- Experience with UPF/CPF based power aware verification.
- Experience with Synopsys NLP (native Low Power) tool.
Our estimated salary range is $120,000 - $180,000 per year, depending on experience and qualifications. We also offer competitive benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off.
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