Lead DFT Engineer
1 week ago
Job Title: Lead DFT EngineerExperience: 7+ YearsLocation: BangaloreEmployment Type: Full-timeIndustry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.Key Responsibilities:- Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.- Lead implementation and verification of DFT features like:- Scan insertion and compression (e.g., EDT)- ATPG pattern generation and fault grading- MBIST and Logic BIST insertion and validation- Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)- Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.- Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.- Perform pattern generation, fault simulation, and debug test coverage gaps.- Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.- Support silicon bring-up, test vector validation on ATE, and yield optimization.- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.- Develop and maintain DFT automation scripts and infrastructure.Required Skills and Experience:- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.- 7+ years of experience in DFT for complex ASIC or SoC designs.- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.- Hands-on experience with DFT tools such as:- Synopsys: DFT Compiler, TetraMAX, TestMAX- Siemens EDA: Tessent ScanPro, MBIST, IJTAG- Cadence/others: Modus, Encounter Test- Strong knowledge of RTL design, STA, and synthesis flows.- Proficient in scripting languages (Python, Perl, Tcl) for flow automation.- Deep understanding of silicon test challenges and test coverage improvement.- Strong leadership, team collaboration, and communication skills.Preferred Qualifications:- Experience with hierarchical DFT and low-power DFT methodologies (UPF).- Exposure to post-silicon validation and failure analysis.- Familiarity with safety-critical designs (ISO 26262) and functional safety.- Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?- Lead DFT for high-performance, next-gen SoCs and ASICs.- Collaborate with top-tier engineers and global semiconductor leaders.- Competitive salary, leadership exposure, and fast-track growth opportunities.Interested can share CV to
-
Lead DFT Engineer
3 days ago
Delhi, India ACL Digital Full timeJob Title: Lead DFT Engineer Experience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC Design Job Summary: We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...
-
Lead dft engineer
1 day ago
Delhi, India ACL Digital Full timeJob Title: Lead DFT EngineerExperience: 7+ YearsLocation: BangaloreEmployment Type: Full-timeIndustry: Semiconductors / ASIC / So C DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex So C/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...
-
Lead DFT Engineer
3 days ago
Delhi, India ACL Digital Full timeJob Title:Lead DFT EngineerExperience:7+ YearsLocation:BangaloreEmployment Type:Full-timeIndustry:Semiconductors / ASIC / SoC DesignJob Summary:We are looking for aLead DFT Engineerto drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional...
-
Lead DFT Engineer
16 hours ago
New Delhi, India eInfochips (An Arrow Company) Full timeWe are hiring for DFT Engineers. Experience- 5+ years Location- Bangalore, Ahmedabad, Hyderabad, NoidaEducational Qualification(s) BE/ME *Detailed Description of the Job Profile • Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis...
-
DFT Lead
1 week ago
New Delhi, India Advanced Micro Devices, Inc Full timeWHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create...
-
High Salary: Lead DFT Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeJob Title: Lead DFT EngineerExperience: 7+ YearsLocation: BangaloreEmployment Type: Full-timeIndustry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...
-
DFT Engineers
4 weeks ago
New Delhi, India Cyient Semiconductors Full timeLead & Mid-Level DFT Engineers – Multiple OpeningsPositions: Mid-Level:4–10 years experience Lead:10+ years experienceAbout the Role: Are you ready todrive the development of Design-for-Test (DFT) strategiesfor advanced SoCs? We are looking forLead and Mid-Level DFT Engineersto contribute to and shape DFT methodologies from concept to silicon, working on...
-
DFT Engineer
3 days ago
Delhi, India Ms Angel and Genie (Talent Search Company) Full timeJob DescriptionWe are looking for an energetic, passionate and process oriented DFT Engineers who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to,working on various aspects of IP and SoC DFT including the DFT Architecture, Spyglass DFT, RTL...
-
DFT Lead Engineer
3 days ago
New Delhi, India 7Rays Semiconductors Full timeJob Description-- The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these. - The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts. - Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and...
-
Senior DFT Engineer and Lead DFT
1 week ago
New Delhi, India Capgemini Engineering Full timeRole: DFT Engineer Experience: 4 to 12 Years Location: BengaluruJob Description:Will be responsible for Designing and Implementing DFT techniques. Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability. Test Modes...
