Design Verification Engineer

1 month ago


bangalore, India UST Full time
Hi ,
Greetings ....
We are hiring for an DV Engineer for one of our reputed client.
Role: DV Engineer
Location: Malaysia /Bangalore
Experience _5-8 years
Skills
Job Description:
Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.
Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols.
Will be part of a team that handles Verification for complex IP’s and close the Verification to the challenging milestones.
IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creation
Support in building verification infrastructure at the chip level as per the requirements
Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level Verification
Working with the team and functional leads; Some interaction with cross functional groups.

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