Digital Verification Engineer M/F

RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions). Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

RISC-V Verification: Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development: Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and...

RISC-V Verification:Lead the verification of RISC-V processor cores, ensuring compliance with the RISC-V ISA specifications (e.g., RV32/64/128, Privileged Architecture, Custom Extensions).Testbench Development:Design, implement, and maintain reusable, scalable, and efficient testbenches using SystemVerilog, UVM (Universal Verification Methodology), and other...

Job Title: IP Verification Engineer – UVM verificationExp Level:4+ yrsLocation: Bangalore/HyderabadJob Description: System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip...

Senior Design Verification EngineersExperience : 5-6 yearsLocation : BangaloreJob Description: Title: OS engineer with 5 to 6years of Experience in SoC DV Role and Responsibilities: a. Individual Contributor b. To understand the design spec, features, SoC requirements and verify the design accordingly. c. Owning 200 to 250 attributes/scenarios per...

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++• Experienced with Verilog, System Verilog, and C or C++• Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. ACL Digital, a leader in...

Senior Design Verification Engineer Experience : 5-6 years Location : Bangalore & Hyderabad Responsibilities:  a. Individual Contributor b. To understand the design spec, features, SoC requirements and verify the design accordingly. c. Owning 200 to 250 attributes/scenarios per project d. Ensure functional coverage , Code coverage is closed 100%...

Senior Design Verification EngineersExperience : 5-6 yearsLocation : BangaloreJob Description: Title: OS engineer with 5 to 6years of Experience in So C DV Role and Responsibilities: a. Individual Contributor b. To understand the design spec, features, So C requirements and verify the design accordingly. c. Owning 200 to 250 attributes/scenarios per...

Formal Verification Engineer Experience : 4 to 12 Years Automate formal flows using scripting (Python, Perl, or Tcl). Document verification plans, results, and sign-off reports. ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise...