Physical Verification

Experience of 5+ years in Physical verification and closure. Location: Bangalore NP - Immediate Main responsibility of the candidate will be around achieving a clean GDS view with below key items: Physical Verification closure for Arm CPU implementation: Should have completed multiple tape-outs with Physical Verification closure role in the past...

Mirafra Technologies Hiring Physical Verification _ SVRF Expert Engineers:Experience - 5 to 15 yearsNotice Period - 0 to 60 daysLocation - BangalorePlease find the Job Description Below:Knowledge, Skills and Experience:5+ years of DRC/LVS development and support experience required. Exceptions made for the right candidates.Good knowledge of CMOS fundamentals...

BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows for power, Ansys Redhawk /Cadence Voltus experience is must Experience – 6+ years Well versed with the power grid design and power calculation methodologies Role involves tasks in estimating power using industry standard tool ,...

Job Summary: We are seeking a highly experienced Senior Physical Design Engineer with over 10 years of experience in the RTL to GDS flow. This full-time role will be based in Bangalore Karnataka. The ideal candidate will possess strong scripting skills, have hands-on experience with 3nm, 5nm nodes, and have a proven track record in physical design. Key...

Job Summary: We are seeking a highly experienced Senior Physical Design Engineer with over 10 years of experience in the RTL to GDS flow. This full-time role will be based in Bangalore Karnataka. The ideal candidate will possess strong scripting skills, have hands-on experience with 3nm, 5nm nodes, and have a proven track record in physical design.Key...

Experience - 7+years Location - Hyderabad, Bangalore, Pune and Kochi Notice Period - Immediate to 60 Days JD Physical Design - • In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. • Should have experience on Physical...

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing...

Role Overview:Job Title : PNR LeadExperience : 8+ YearsWork location : BangaloreJob Description:Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks...

Experience with industry-standard physical design tools (Cadence, Synopsys, Mentor Graphics)Knowledge of advanced process nodes (7nm, 5nm, etc.)Experience with scripting languages such as Python, TCL, or PerlStrong understanding of VLSI design principlesExperience in low-power design techniquesBachelor's or Master's degree in Electrical Engineering or...

Should be able to handle Full chip hashtagAdded advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag#IO ring,#package support, multi hashtag#voltage design.🔸Deep understanding of the concepts related to hashtag#synthesis, place & route, hashtag#CTS, timing convergence, IR/EM checks and signoff DRC/LVS...