Cpu design verification engineer
1 week ago
CPU Test Bench DV Engineer
- Responsibilities
- Design, develop, and maintain parameterizable core and cluster testbench environments (C++ and Synthesizable SV) for a RISCV CPU family
- Build key testbench components including harnesses, checkers, transactors, models and miscellaneous items like preloaders, trickbox, randomization etc
- Contribute to C++ methodology framework that incorporates modern C++ features, to ease writing of testbench components - CVM (UVM for C++)
- Work with environments that are portable across simulators (including open source verilator) and emulation platforms
- Support the core and cluster DV teams with bringing up arch and micro-arch features
- Develop tools and innovative solutions to simplify debug of simulation/emulation failures
- Experience and Qualifications
- Bachelors/Masters in ECE/CS with at least 7 years of experience
- Proficiency in C++ and SV programming languages
- Good understanding of the fundamentals behind a DV methodology like UVM
- Good understanding of software engineering concepts, like publisher-subscriber patterns, multi-threaded programming, co-routines, etc
- Knowledge of any CPU architecture (x86, ARM, RISCV) and basic micro-architecture
- Solid problem-solving skills and the ability to analyze across layers of abstraction stack from high level software code to low level assembly programs to RTL implementation code
- Excellent communication skills and the ability to work effectively in a team environment
- Eagerness to learn and adapt to new challenges in a fast-paced, dynamic environment
Locations: Bangalore, India
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
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