CPU/Processor Verification

3 months ago

Bengaluru, India Mulya Technologies Full time
CPU/Processor Verification - FabricFortune 100 OrganizationLocation: Bangalore / Hyderabad

Introduction

CPU/Processor Verification - Fabric

Introduction

As a Hardware Developer at you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable our customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role and Responsibilities

As a CPU Verification Engineer, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation Power Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Electronics / Micro Electronics / Computer Science with strong programming skills is required.

Your Role And Responsibilities

As a CPU Verification Engineer, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, memory hierarchy, and various on-silicon IP integral to our upcoming Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems.

Key Duties

Verification Environment Ownership: Take charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes.

Documentation and Communication: Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered. Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in Server Processors.

Required Technical and Professional Expertise

Functional Verification Experience: Extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies.Computer Architecture Knowledge: Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains.Multi-processor Cache Coherency Transport Fabric : Experience in functional verification of system level Coherency Transport Network designs and ways to stress verify them.Strong programming skills: Proficiency in C++, Python scripting or similar languages.

Preferred Technical And Professional ExpertiseExperience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts.Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design.Experience in specifying and developing the verification infrastructure for verifying processor based designs.Minimum one full life cycle experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect/Fabric Verification.Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects

Contact:UdayMulya "Mining The Knowledge Community"

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