Senior Design Verification Lead

2 days ago

Delhi, India Eximietas Design Full time

Company:Eximietas Design... Hiring: Senior Design Verification (PCIE) Engineers / Leads / Managers.Experience:8-20+ YearsLocations:Bengaluru, IndiaVisakhapatnam, IndiaSan Jose (Bay Area), USAAustin, USAEligibility (US Roles): Valid H1B or candidates already in the U.S.Job Description:#Lead SoC Design Verification efforts for complex projects, ensuringsuccessful execution of verification plans.#Develop and implement comprehensive verification strategies, includingtest plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM).#Conduct Gate-level simulations and power-aware verification using toolslike Xprop and UPF.#Collaborate closely with cross-functional teams, including architects,designers, and pre/post-silicon verification teams, to ensure alignmentand seamless integration of verification efforts.#Analyze and implement System Verilog assertions and functionalcoverage (code, toggle, functional) to ensure thorough verification of designfunctionality.#Provide mentorship and technical guidance to junior verification engineers,helping to elevate team performance.#Lead and manage a dynamic team of verification engineers, fostering acollaborative and innovative work environment.#Ensure that all verification signoff criteria are met, with clear andcomprehensive documentation.#Demonstrate strong dedication, work ethic, and commitment to meetingproject goals and deadlines.#Uphold quality standards and implement best test practices, contributing tocontinuous improvements in verification methodologies.#Work with verification tools from Synopsys and Cadence, including VCSand Xsim.# I ntegrate third-party VIPs (Verification IP) from Synopsys and Cadence toenhance verification coverage.Qualifications:8+ years of hands-on experience in SoC Design Verification.#Expertise in verification of high-speed SoCs and various protocols, includingI2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, andHBM.#Proficiency in System Verilog for verification, including assertions andcoverage.#Experience with gate-level simulations and power-aware verification usingXprop and UPF.#Strong hands-on experience with VCS and Xsim from Synopsys andCadence.#Mentorship experience, providing guidance to junior engineers andmanaging verification teams.#Demonstrated ability to work with cross-functional teams, ensuring effectivecollaboration and verification signoff.#Strong understanding of verification methodologies and ability to contributeto their continuous improvement.Preferred Qualifications:#Experience in third-party VIP integration (Synopsys/Cadence).#Prior experience in leading large verification teams and projects.#Familiarity with pre/post-silicon verification processes.Interested Engineers, please share your updated resume: are greatly appreciated—please feel free to forward this within your network...Best regards,Maruthy PrasaadAssociate VLSI Manager - Talent Acquisition | VisakhapatnamEximietas .

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