Senior Design Verification Lead

5 hours ago

New Delhi, India Eximietas Design Full time

Eximietas Hiring Senior Design Verification Engineers/Leads (PCIE) Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US.Job Description: LeadSoC Design Verificationefforts for complex projects, ensuring successful execution of verification plans. Develop and implementcomprehensive verification strategies , including test plans, testbenches, and coverage analysis, for bothhigh-speedandlow-speed peripherals(e.g., I2C, SPI, UART, GPIO, QSPI) as well ashigh-speed protocols(e.g.,PCIe, Ethernet, CXL, MIPI, DDR, HBM ). ConductGate-level simulationsandpower-aware verificationusing tools likeXpropandUPF . Collaborate closely with cross-functional teams, includingarchitects, designers , andpre/post-silicon verification teams , to ensure alignment and seamless integration of verification efforts. Analyze and implementSystem Verilog assertionsandfunctional coverage(code, toggle, functional) to ensure thorough verification of design functionality. Providementorshipandtechnical guidanceto junior verification engineers, helping to elevate team performance. Lead and manage a dynamic team of verification engineers, fostering acollaborativeandinnovative work environment . Ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Demonstrate strong dedication, work ethic, and commitment to meetingproject goalsanddeadlines . Upholdquality standardsand implementbest test practices , contributing to continuous improvements in verification methodologies. Work withverification toolsfromSynopsysandCadence , includingVCSandXsim . Integratethird-party VIPs(Verification IP) fromSynopsysandCadenceto enhance verification coverage.Qualifications: 8+ years of hands-on experienceinSoC Design Verification . Expertise in verification ofhigh-speed SoCsand various protocols, includingI2C/I3C ,SPI ,UART ,GPIO ,QSPI ,PCIe ,Ethernet ,CXL ,MIPI ,DDR , andHBM . Proficiency inSystem Verilogfor verification, includingassertionsandcoverage . Experience withgate-level simulationsandpower-aware verificationusingXpropandUPF . Strong hands-on experience withVCSandXsimfromSynopsysandCadence . Mentorshipexperience, providing guidance to junior engineers and managing verification teams. Demonstrated ability to work withcross-functional teams , ensuring effective collaboration and verification signoff. Strong understanding ofverification methodologiesand ability to contribute to their continuous improvement.

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