SeniorPrincipal ASIC RTL Design Engineer

2 hours ago

Bangalore, India Proxelera Full time

Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. ~ Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. ~ Drive design reviews, close bugs, and support silicon validation and post-silicon debug. ~ 10+ years of hands-on ASIC RTL development experience (FPGA work does not count toward the 10 years). ~ Strong SystemVerilog/Verilog RTL and micro-architecture skills, including clock/reset design, low-power techniques (UPF/retention/isolation), and AMBA/standard bus protocols (AXI/ACE/AHB/APB). ~ Proven collaboration with physical design on synthesis constraints, timing closure, DFT hooks, and ECOs. ~ Proven silicon bring-up experience for owned blocks/subsystems. SVA for design-level assertions, performance modeling, or power/perf analysis skills. Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work.

  • SeniorPrincipal ASIC RTL Design Engineer

    2 days ago

    bangalore, India Proxelera Full time

    Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...

  • SeniorPrincipal ASIC RTL Design Engineer

    1 day ago

    Bangalore, India Proxelera Full time

    Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: - Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. - Own design bring-up, block/subsystem integration, and close on...

  • SeniorPrincipal ASIC RTL Design Engineer

    1 day ago

    Bangalore Urban, India Proxelera Full time

    Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. Own design bring-up, block/subsystem integration, and close on timing,...

  • SeniorPrincipal ASIC RTL Design Engineer

    2 days ago

    Bangalore Urban, India Proxelera Full time

    Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...

  • ASIC RTL Integration Engineer

    2 days ago

    Bangalore, India DevloiT Full time

    Position: ASIC RTL Integration / ASIC RTL Coding Location: Bangalore, India Employment Type: Long Term Contract Minimum Experience: 4 Years+ About the Role: We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of...

  • ASIC SOC RTL Design Lead

    2 days ago

    Bangalore, India Eximietas Design Full time

    Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly...

  • ASIC RTL Integration Engineer

    3 days ago

    bangalore, India DevloiT Full time

    Position: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...

  • ASIC RTL Integration Engineer

    3 days ago

    bangalore district, India DevloiT Full time

    Position: ASIC RTL Integration / ASIC RTL Coding Location: Bangalore, India Employment Type: Long Term Contract Minimum Experience: 4 Years+ About the Role: We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of...

  • (Apply Now) ASIC SOC RTL Design

    2 weeks ago

    Bangalore, India Eximietas Design Full time

    Hi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Hiring: Senior ASIC SOC RTL Design Engineers. Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in...

  • ASIC RTL Design Engineer

    3 weeks ago

    bangalore, India ACL Digital Full time

    ASIC RTL Design Engineer Location : Bangalore Job Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...