SeniorPrincipal ASIC RTL Design Engineer
1 day ago
Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. Drive design reviews, close bugs, and support silicon validation and post-silicon debug. Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 10 years). Must-have qualifications: 10+ years of hands-on ASIC RTL development experience (FPGA work does not count toward the 10 years). Multiple production ASIC tapeouts owning significant SoC or subsystem functionality (e.g., interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands). Strong SystemVerilog/Verilog RTL and micro-architecture skills, including clock/reset design, low-power techniques (UPF/retention/isolation), and AMBA/standard bus protocols (AXI/ACE/AHB/APB). Proven collaboration with physical design on synthesis constraints, timing closure, DFT hooks, and ECOs. Proven silicon bring-up experience for owned blocks/subsystems. Nice to have: Exposure to coherency protocols, cache/memory controllers, DDR/PCIe subsystems, security/crypto blocks. SVA for design-level assertions, performance modeling, or power/perf analysis skills. Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work.
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SeniorPrincipal ASIC RTL Design Engineer
2 days ago
Bangalore Urban, India Proxelera Full timeSummary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...
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SeniorPrincipal ASIC RTL Design Engineer
1 day ago
Bangalore, India Proxelera Full timeSummary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: - Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. - Own design bring-up, block/subsystem integration, and close on...
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SeniorPrincipal ASIC RTL Design Engineer
2 days ago
bangalore, India Proxelera Full timeSummary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...
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SeniorPrincipal ASIC RTL Design Engineer
2 hours ago
Bangalore, India Proxelera Full timeSummary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. ~ Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. ~ Drive...
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ASIC RTL Integration Engineer
2 days ago
Bangalore, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL Coding Location: Bangalore, India Employment Type: Long Term Contract Minimum Experience: 4 Years+ About the Role: We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of...
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ASIC SOC RTL Design Lead
2 days ago
Bangalore, India Eximietas Design Full timeHi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly...
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ASIC RTL Engineer 4+ years Bangalore
3 weeks ago
Bangalore Urban, India ACL Digital Full timeRTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems.Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...
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ASIC RTL Integration Engineer
3 days ago
bangalore, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
3 days ago
bangalore district, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL Coding Location: Bangalore, India Employment Type: Long Term Contract Minimum Experience: 4 Years+ About the Role: We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of...
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(Apply Now) ASIC SOC RTL Design
2 weeks ago
Bangalore, India Eximietas Design Full timeHi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Hiring: Senior ASIC SOC RTL Design Engineers. Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in...
