BITSILICA | Senior Physical Verification | bangalore

About the Company Bitsilica is a company that specializes in physical design implementation of large ASIC’s. Our mission is to provide cutting-edge solutions in the semiconductor industry while fostering a culture of innovation and collaboration. About the Role We are looking for a candidate with relevant work experience in physical design implementation...

About the Company Bitsilica is a company that specializes in physical design implementation of large ASIC’s. Our mission is to provide cutting-edge solutions in the semiconductor industry while fostering a culture of innovation and collaboration.About the Role We are looking for a candidate with relevant work experience in physical design implementation of...

Hello Connections,We are currently Hiring Senior Physical Verification Engineers - 5+yrs Location: BengaluruAvailability - Immediate to 20 Days Job Description:1.Experience on PV closure and tape out for 7ff or below tech node.2.Good understanding of advance design rule and fixes3.Experience in Calibre and Innovus is mandatory4.Block level PV closure at...

About the Company Bitsilica is a company that specializes in physical design implementation of large ASIC’s. Our mission is to provide cutting-edge solutions in the semiconductor industry while fostering a culture of innovation and collaboration. About the Role We are looking for a candidate with relevant work experience in physical design...

Hi All,We have an excellent opportunity #Bitsilica #BangaloreLooking for an Experienced Robotics Engineer to design robotics devices software and applications. Deep knowledge in robotics, machine vision, automation concepts, computer systems and exceptional programming skill.Responsibilities1. Design and develop industrial robotics2. Understanding Fleet...

Hi All, We have an excellent opportunity #Bitsilica #Bangalore Looking for an Experienced Robotics Engineer to design robotics devices software and applications. Deep knowledge in robotics, machine vision, automation concepts, computer systems and exceptional programming skill. Responsibilities 1. Design and develop industrial robotics 2. Understanding Fleet...

Hi All,We have an excellent opportunity #Bitsilica #BangaloreLooking for an Experienced Robotics Engineer to design robotics devices software and applications. Deep knowledge in robotics, machine vision, automation concepts, computer systems and exceptional programming skill.Responsibilities1. Design and develop industrial robotics2. Understanding Fleet...

Email me - Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and...

Location: Bengaluru/Bangalore Experience: 3yrs to 10 yrs Notice Period: Immediate to 30 Days Job Description: • 3 to 8 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (16nm to 130nm ) • Expertise in Cadence GXL / XL and Mentor Graphic Calibre DRC / LVS / PEX is a must. • Should have hands on...

About the Role - Lead AMS IP/chip verification, including reviewing design specifications and defining and executing a verification plan to ensure compliance with specifications. Architect, implement, and automate analog, digital, and AMS test benches to verify pre-silicon designs. Build System Verilog real number analog behavioral models, monitors, and...

RTL - Bangalore and Noida 7+ year experience candidate with following criteria Expertise and hands on experience in Verilog/RTL design for IP or SoC. Command and thorough knowledge on digital logic design concepts. Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture. Must have experience in...

RTL - Bangalore and Noida7+ year experience candidate with following criteriaExpertise and hands on experience in Verilog/RTL design for IP or SoC.Command and thorough knowledge on digital logic design concepts.Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.Must have experience in...

RTL - Bangalore and Noida7+ year experience candidate with following criteriaExpertise and hands on experience in Verilog/RTL design for IP or SoC.Command and thorough knowledge on digital logic design concepts.Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.Must have experience in...

Email me - afreen.malik@bitsilica.com Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks,...

Email me - Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and System Verilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and...

Email me - Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flowProficient with Verilog, System Verilog and UVM.· Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard)· Good in defining and developing UVM based verification frameworks, testbenches, processes and flows.·...

Location: BengaluruExperience: 2+yrsJob Description:LIB timing file generationVerilog ModellingAnalog design characterization - familiarity with Cadence spectre and Synopsys HspiceAdditional help with Analog Quality ChecksEM/IR simulationPlease share your profile to afreen.malik@bitsilica.com

Location: Bengaluru Experience: 2+yrs Job Description: LIB timing file generation Verilog Modelling Analog design characterization - familiarity with Cadence spectre and Synopsys Hspice Additional help with Analog Quality Checks EM/IR simulation Please share your profile to

Location: BengaluruExperience: 2+yrsJob Description:LIB timing file generationVerilog ModellingAnalog design characterization - familiarity with Cadence spectre and Synopsys HspiceAdditional help with Analog Quality ChecksEM/IR simulationPlease share your profile to

Email me - Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and...