Senior Memory Circuit Designer

2 weeks ago

Dombivli, Maharashtra, India beBeeDesign Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Job Summary:

We are seeking a highly skilled Memory Design Engineer to join our team.

The ideal candidate will have hands-on experience with full custom memory design and architectures, characterization, layout design, net-listers, and complete SRAM design verification at the compiler level.

A key responsibility will be to ensure the execution plan, design quality plan, DFMEA, and project health are populated and published. Regular reporting of risks and mitigation strategies is also required.

The successful candidate will possess good knowledge of different types of memory architecture and have hands-on experience in SRAM leaf cell GDS from scratch to top-level integration.

Key Responsibilities:

  • To create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler.
  • Expertise in working on memory layout design for advanced nodes (TSMC: 7nm/5nm/3nm) is mandatory.
  • Proficiency in physical verification flow debug tools such as DRC, LVS, DFM, PERC, ERC, EM, IR is necessary.
  • Cadence Virtuoso layout editor and Caliber Physical Verification Flow expertise is also required.
  • Synopsys Custom Compiler experience is a significant plus.
  • Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm are essential.
  • Experience in optimizing layouts for yield enhancement and manufacturing robustness, debugging silicon failures, and identifying layout-related issues is also required.
  • Expertise in working on FinFET architecture and challenges such as variability and manufacturability is necessary.

Requirements:

  • Hands-on experience with full custom memory design and architectures
  • Characterization, layout design, net-listers, and complete SRAM design verification at the compiler level
  • Execution plan, design quality plan, DFMEA, and project health population and publishing
  • Risks and mitigation strategies regular reporting
  • Good knowledge of different types of memory architecture
  • SRAM leaf cell GDS from scratch to top-level integration experience
  • Memory layout design for advanced nodes (TSMC: 7nm/5nm/3nm)
  • Physical verification flow debug tools (DRC, LVS, DFM, PERC, ERC, EM, IR) proficiency
  • Cadence Virtuoso layout editor and Caliber Physical Verification Flow expertise
  • Synopsys Custom Compiler experience
  • Good layout practices in lower process nodes knowledge
  • LAYOUT OPTIMIZATION FOR YIELD ENHANCEMENT AND MANUFACTURING ROBUSTNESS EXPERIENCE
  • FinFET architecture and challenges expertise

About Us:

We offer a dynamic work environment that promotes collaboration, innovation, and growth. Our team is passionate about delivering high-quality solutions that meet the needs of our clients.

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