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R&D Engineer Lead

1 week ago

Noida, Uttar Pradesh, India Synopsys Inc Full time
Job Description

- **Experience:** 3-7 years of experience in verification engineering
- Expertise in UVM and System Verilog, with a focus on verification IP modeling and test case coding.
- Proficient in scoreboard design, assertions, checkers & functional coverage, with the ability to contribute to the development of reusable Verification environments using VMM/OVM/UVM methodologies.
- Protocol Experience: Strong understanding of UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocols, with experience in driving resolution on issues from an architecture/methodology perspective.

- Contribute to the development of Verification Intellectual Property (VIP)
- Responsible for review sign-off of VIP development and updates from a technical perspective, including methodology and protocol functional prospective.
- Collaborate with Architects/methodology experts to achieve resolutions on issues or drive output from an architecture/methodology perspective.
- Serve as a 'go-to' person on all technical aspects of VIP within the team.

Company Overview
Synopsys Inc is a leading provider of electronic design automation (EDA) software and services. Our company empowers innovators around the world to realize their visions of innovation through the use of our cutting-edge technologies and solutions.

Job Responsibilities
The ideal candidate will have a strong background in verification engineering, with expertise in UVM and System Verilog. The successful candidate will be able to contribute to the development of reusable Verification environments and drive resolution on issues from an architecture/methodology perspective.