Cutting Edge Designer for Complex Systems

1 week ago

Bengaluru, Karnataka, India beBeeDesignForTest Full time ₹ 5,00,000 - ₹ 8,00,000
Design-for-Test Engineer

As a key member of our team, you will be responsible for developing and implementing Design-for-Test (DFT) features for cutting-edge products. Your expertise in DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST will be instrumental in ensuring the quality and reliability of our designs.

About the Role
  • You will work with a team of design engineers to develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications.
  • Your responsibilities will include performing DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS.
  • You will also be responsible for developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
  • In addition, you will perform scan insertion, ATPG verification and test pattern generation, as well as providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.
Requirements
  • Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus.
  • Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST.
  • Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
  • Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations.
  • Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc.
  • Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl).
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language.
  • Familiar with Verilog design language, Verilog simulator and waveform debugging tools.
  • Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus.
  • Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc. is a plus.
  • Strong problem-solving skills.
  • Team player with strong communication skills.
Credentials
  • Bachelors or Masters degree in computer engineering/Electrical Engineering.

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