Digital Memory Chip Architect

1 week ago

Dholera, India beBeeMemory Full time ₹ 1,50,00,000 - ₹ 2,09,50,000

Imagine working on cutting-edge technology that powers the next generation of electronics. As a Bitcell Layout Design Engineer, you will be at the forefront of this revolution.

We are seeking an exceptional individual with expertise in memory bit cell and array layout to spearhead our eNVM development. In this role, you will be responsible for designing, optimizing, and verifying eNVM bitcells across various foundry processes.

Your key responsibilities will include:

  • Designing eNVM bitcell layouts for wide range of foundry processes (130nm to 28nm & FinFET)
  • Creating, optimizing, and verifying bitcell kits for each eNVM
  • Root cause analysis of problems with devices and bitcells, documenting test structures
  • Driving improvement of infrastructure for bitcell kit and SLM creation and verification
  • Evaluating foundry PDK changes, providing expert advice to design team on impact on eNVM design
  • Analysis of incoming mask sets with respect to memory bitcell content

You will work closely with design and layout teams to fix or justify waiving violations, keeping track of changes across design manual. Your basic understanding of ESD and latch-up prevention techniques will enable you to advise design and layout teams effectively.

To succeed in this role, you should have:

  • 5-10 years' experience in semiconductor industry
  • Bachelor's, Master's, or PhD in microelectronics, semiconductor physics, or related fields
  • Ideal 5-10 years of experience with emphasis on memory bit cell and array layout and characterization of memory bit cells
  • Proficient use of common EDA tools like Cadence or Calibre for layout design, including verification by DRC and LVS etc.
  • Basic knowledge of functionality of memory bit cells and arrays like SRAM, MRAM, RRAM
  • Knowledge and good understanding of components included in PDK
  • Experience with bench measurement is preferred
  • Good understanding of planar and FinFET CMOS flows is preferred

In addition to your technical expertise, we are looking for individuals who are:

  • Strong leaders with experience mentoring and motivating high-performing teams
  • Effective communicators and collaborators across global, cross-functional groups
  • Inclusive and adaptable to diverse cultural and professional environments
  • Curious, resilient, and data-driven in approaching challenges
  • Builders of strong relationships and offer support with humility
  • Innovative and agile, quick to explore new ideas and embrace change

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