
Senior DFT Specialist
2 weeks ago
Job Title: Digital Fault Tolerance Architect
The Digital Fault Tolerance (DFT) Engineer will be responsible for developing and implementing DFT architecture for complex IC designs. This role requires a strong understanding of digital design principles, DFT techniques, and ATPG tools.
- Develop and implement DFT architectures for ASIC/SoC designs, ensuring seamless integration with RTL and physical design teams.
- Insert and verify scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures to ensure optimal test quality.
- Collaborate with cross-functional teams to optimize test programs and support production testing.
Key Responsibilities:
- Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
- Perform fault simulation and coverage analysis to optimize test quality.
- Support silicon bring-up and debug of test-related issues.
Requirements:
- 3+ years of experience in DFT engineering.
- Strong understanding of digital design principles, DFT techniques, and ATPG tools.
- Excellent collaboration and communication skills.
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