Advanced Semiconductor Architectural Designer

2 weeks ago

Bengaluru, Karnataka, India beBeePhysicalDesign Full time US$ 1,50,000 - US$ 2,00,000

Job Title: SOC Physical Design Manager

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As a Senior PD Manager, you will drive the implementation and execution of next-generation SOCs. You will lead a team of engineers responsible for end-to-end physical design execution from RTL to GDSII. Collaborate closely with SOC architects, physical design architects/leads, and IP teams to achieve first-pass silicon success.

The Ideal Candidate:

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  • You will have 18+ years of experience in managing physical design execution across RTL to GDSII, PnR, STA, and physical verification.
  • Experienced in block-level implementation (Place and Route), including Floorplanning, Timing Closure, and Physical Verification.
  • Well-versed in physical design verification signoff techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), and Physical Verification.
  • Excellent communication and presentation skills.

About the Role:

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You will be responsible for leading a team of silicon design engineers for successful project tape-outs from RTL-GDSII. Use your knowledge of physical design to drive backend activities, specifically PnR, timing, verification, and signoff including IP integration and full-chip aspects. A detail-oriented leader with strong self-driving ability and winning attitude is required. The ideal candidate should have excellent communication and presentation skills demonstrated through technical publications, presentations, trainings, and executive briefings.

Key Responsibilities:

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  • Lead a team for the implementation and convergence of highly complex multi-million gate tiles, subchip, and SOC full chip.
  • Responsible for delivery of GDSII starting from RTL, including Signoff and physical verification.
  • Collaborate with cross-functional teams to drive continuous improvements for achieving better PPA.
  • Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full-chip integration flows.
  • Understanding design requirements, timelines, and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle.
  • Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology.
  • Strong interpersonal skills to work across teams in different geographies.
  • Provide technical direction, guidance, and support to the engineering team.
  • People management, goal setting, assessment, calibration, appraisal, and improvement plan.

Required Qualifications:

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  • B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering.
  • 15+ years of experience in PD execution.
  • Candidate must have the ability to drive/manage projects from RTL to GDSII, with a minimum experience of managing more than 2 SOC tape-outs.
  • Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power, and physical verification tools.

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