VLSI Design Verification Engineer
3 days ago
About L&T Technology Services
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- As a leading global technology consulting and digital solutions company, we empower our clients to succeed through the effective use of technology.
Job Overview
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- We are expanding our Digital Verification (DV) team in the Semiconductors practice at LTTS, and we are seeking experienced DV engineers with strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
Key Responsibilities
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- Develop and execute complex verification environments using SV/UVM primarily for PCIe protocol coverage models.">
- Coverage analysis, regression failure triage, and testbench bug fixes are key aspects of this role.">
- Bring up and debug of xprop, 0-delay gate-level simulations, and power simulations will also be involved.">
- The successful candidate may also participate in integration qualification of subunit designs/models and Virtual Integration Protocol (VIP) in unit DV environments.
Requirements
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- A minimum of 2-5 years of experience in VLSI design verification, preferably with expertise in SV/UVM.">
- Strong understanding of PCIe protocol, including physical and data link layers.">
- Familiarity with coverage model development and analysis.">
- Excellent problem-solving skills and ability to work in a fast-paced environment.
What We Offer
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- A competitive salary range of $120,000-$180,000 per annum, based on location and experience.">
- Ongoing training and professional development opportunities.">
- A collaborative and dynamic work environment.
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