Principal/Staff Engineer Rtl Design Pcie/Cxl
3 weeks ago
Marvell's semiconductor solutions are the foundation of the data infrastructure that connects our world. Across enterprise, cloud, and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can shape the arc of individual lives, elevate the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those seeking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactThe Custom and Compute Solutions Business Unit collaborates closely with strategic customers in the development of advanced and highly complex SoCs, from architecture and design through layout, packaging, prototype validation, and production ramp-up.
What You Can Expect- Define the sub-system architecture, micro-architecture, and register specification for highly complex SoCs.
- Drive and participate in specification write-up.
- Conduct detailed performance, architectural, and design requirement reviews with cross-functional teams, IP vendors, and customers.
- Implement a specification using RTL coding techniques and best practices.
- Work with third-party vendors to define customization requirements of third-party IPs (controller, PHY, etc.).
- Work with physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis, and timing sign-off.
- Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation, and emulation, performance, and power analysis, and debug.
- Help develop and/or evaluate design and verification methodologies and participate in improving existing ones.
- Collaborate with and provide guidance to the post-silicon and software teams for prototype bring-up and performance tuning.
- Provide mentorship to more junior team members.
We're seeking a highly skilled and experienced engineer with a strong background in RTL design, architecture, and verification. The ideal candidate will have a bachelor's degree in Computer Science, Electrical Engineering, or a related field, and 7-18 years of related professional experience. A master's degree and/or PhD in Computer Science, Electrical Engineering, or a related field with 6-18 years of experience is also acceptable.
The successful candidate will have experience in creating architectural, micro-architectural, and register specifications, as well as Verilog/System Verilog RTL coding with System Verilog assertions. They will also be well-versed in all stages of the ASIC design flow, including specification, architecture, and design implementation, prototype bring-up, and high-speed memory protocols (PCIe Gen4/5/6, CXL 2.0/3.1).
Experience with complex chips such as network processors, CPUs, GPUs, NOCs, Switches, Machine Learning SoCs, and owning full-chip, sub-system, and block-level architecture and design is highly desirable. Expertise in any of the following domains would be a significant plus: networking, embedded systems architecture, computer architecture, machine learning accelerators. Experience with scripting in Perl/Python/Shell is also a plus.
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