Senior Staff Engineer
4 weeks ago
In this role, you will be responsible for designing and integrating IPs and SoCs. A self-motivated engineer with experience in RTL design and minimal supervision.
Key Responsibilities:- Perform RTL micro-architecture design and integration for IoT SoCs.
- Integrate sub-systems/IPs while considering sub-system/IP features/configurations/generics, power/clock/reset, and standard/proprietary interface requirements.
- Work with digital/analog/RF IP teams to arrive at IP configuration at SoC level.
- Drive power topology, clock structure, and reset strategy at SoC level.
- Identify low power opportunities at IP/SoC level.
- Arrive at IO requirements/muxing.
- Design SoC infrastructure IP (like power, reset, clocking) micro-architecture.
- Run and analyze RTL quality checks like LINT and CDC.
- Participate in defining power intent of SoC.
- Contribute to synthesis constraints at SoC level.
- Participate in silicon debug activities.
- Help drive improvements on-the-fly in all the above areas.
- Ensure an inclusive teamwork environment.
- B Tech with 7+ years of experience or M Tech with 5+ years of experience in IP Design with few years of experience in SoC design.
- Must have several years of experience in ASIC design flow and mentoring junior engineers.
- Must have expertise on processor-based SoC design including ARM processor, DMAs, power/clock/reset controllers, and interfaces like USB/SDIO/PCIe/SPI/UART.
- Must have good understanding of high-speed interfaces like USB, SDIO, PCIe.
- Expertise in System Verilog/VHDL languages.
- Expertise with scripting.
- Team player with good communication skills.
- Strong analytical and problem-solving skills.
- Familiarity with Security architecture/requirements is a plus.
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