Senior ASIC Design Engineer
2 days ago
As a senior-level Design for Testability (DFT) engineer, you will be responsible for implementing hardware Memory Built-In Self-Test (MBIST) features that support Automated Test Equipment (ATE), in-system test, debug, and diagnostics needs of the memories in design.
Key Responsibilities:- Design and implement MBIST features for memory testing and silicon engineering to ensure high-quality patterns are released to the test team and support silicon bring-up and yield improvement.
- Collaborate closely with cross-functional teams including design, design verification, and backend teams to integrate and validate test logic.
- Utilize scripting skills to design and debug with minimal oversight.
Requirements:
- At least 10 years of experience as an ASIC Design DFT engineer with a broad mix of technologies including knowledge of latest trends in Memory testing and silicon engineering.
- Hands-on experience in Joint Test Action Group (JTAG) & Intelligent JTAG (IJTAG) protocols, MBIST, and scan architectures.
- Verification skills including System Verilog, Language Embedded Compiler (LEC), and validating test timing of the design.
- Experience working with gate-level simulations and debug with VCS and other simulators.
- Understanding of testbench in System Verilog, Universal Verification Methodology (UVM)/VereSatil Model Manager (VMM) (optional).
- Post-silicon validation and debug experience, ability to work with ATE patterns.
- Strong verbal communication skills and ability to thrive in a dynamic environment.
- Scripting skills: Python/Perl.
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