Senior Silicon Design Engineer

7 days ago

Bengaluru, Karnataka, India beBeeSilicon Full time ₹ 45,00,000 - ₹ 55,00,000
Job Title: Senior Silicon Design Engineer">Job Description:

We seek a seasoned silicon design engineer to lead our team in advanced micro devices.

The ideal candidate possesses outstanding analytical and problem-solving skills, excellent communication and presentation abilities, and meticulous attention to power, performance, and area while driving schedule and managing cost.

You will collaborate effectively among top-thinkers and engineers, mentoring and guiding team members to elevate their knowledge and skills.

Key Responsibilities:

  • RTL to GDS2 flow management
  • Physical implementation of floor-plan, power-plan, synthesis, placement, CTS, routing, extraction, timing closure (tile level, full chip), physical verification (DRC LVS), crosstalk analysis, EM/IR
  • Full-chip timing analysis setup and signoff of multi-corner multi-voltage designs, hierarchical timing analysis, and convergence at block, section, and full-chip levels
  • Closely engage with design teams to understand design, constraints, and convergence challenges, providing ECOs with a focus on PPA and TAT optimizations
  • Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Identifying and implementing opportunities for improving PPA

Preferred Experience:

  • 16+ years of professional experience in physical design, full-chip timing, and high-performance designs
  • Experience in areas of timing analysis, timing convergence, SI/Noise analysis, signoff quality (PVT, process variation effects, guardbanding, etc.), timing ECOs, PV/Noise modelling, .libs
  • Automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications
  • Automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
  • Floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
  • Versatility with scripts to automate design flow, proficiency in scripting languages like Perl and Tcl
  • Strong communication skills, ability to multitask across projects, and work with geographically spread-out teams
  • Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm
  • Excellent physical design and timing background
  • Good understanding of computer organization/architecture is preferred
  • Strong analytical/problem-solving skills and pronounced attention to details

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