Senior Principal Test Development Engineer

2 weeks ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Job Title: Senior Design Verification Engineer

 

Job Description

The Senior Design Verification Engineer will be responsible for defining and implementing IP/SoC verification plans, building verification test benches to enable IP/sub-stem/SoC level verification, and driving design verification to closure based on defined verification metrics.

The ideal candidate will have a strong background in computer science or electronics engineering, with 6+ years of experience in StemVerilog/UVM methodology and/or C/C++ based verification. They should also have experience in developing UVM based verification environments from scratch, architecting and implementing design verification infrastructure, and executing the full verification cycle.

In addition, the candidate should have experience with verification of ARM/RISC-V based CPU sub-stems or SoCs, as well as expertise in protocols like AMBA, PCIe, DDR, USB, Ethernet. They should also be proficient in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments, and familiar with revision control stems like Mercurial(Hg), Git or SVN.

The successful candidate will work closely with the design team to debug, root-cause, and resolve functional failures in the design. They should be able to communicate effectively and provide regular updates on project progress.

Key Responsibilities:
  • Define and implement IP/SoC verification plans
  • Build verification test benches to enable IP/sub-stem/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive design verification to closure based on defined verification metrics
  • Debug, root-cause, and resolve functional failures in the design

 

Qualifications and Skills:
  • Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
  • 6/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
  • Experience in development of UVM based verification environments from scratch
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
  • Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
  • Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
  • Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Experience with revision control stems like Mercurial(Hg), Git or SVN
Requirements:

The following requirements must be met by the selected candidate:

  • Strong understanding of computer science or electronics engineering principles
  • Excellent communication and collaboration skills
  • Ability to work in a fast-paced environment and meet deadlines
  • Strong problem-solving and analytical skills

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