Chief Verification Architect

8 hours ago

Hubli, Karnataka, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Title: Senior Design Verification Engineer

  • Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
  • Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  • Write and maintain directed and constrained-random test cases.
  • Perform Gate-Level Simulation (GLS) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
  • Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
  • Validate high-speed protocols, such as PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, and CXL.
  • Debug RTL and testbench issues using waveforms, logs, and assertions.
  • Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
  • Analyze functional/code/line/branch/coverage metrics and drive closure.
  • Automate regressions and result analysis using scripting languages, such as Python, Perl, Shell, or Tcl.
  • Contribute to methodology improvements, tool evaluation, and reusable IP verification components.

Responsibilities:
  1. Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
  2. Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  3. Write and maintain directed and constrained-random test cases.
  4. Perform Gate-Level Simulation (GLS) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
  5. Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
  6. Validate high-speed protocols, such as PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, and CXL.
  7. Debug RTL and testbench issues using waveforms, logs, and assertions.
  8. Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
  9. Analyze functional/code/line/branch/coverage metrics and drive closure.
  10. Automate regressions and result analysis using scripting languages, such as Python, Perl, Shell, or Tcl.
  11. Contribute to methodology improvements, tool evaluation, and reusable IP verification components.

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