
Senior ASIC Verification Expert
5 days ago
Role Overview
We are seeking a skilled Verification Engineer to join our highly experienced ASIC team working on cutting-edge technology nodes. The successful candidate will be responsible for overall IP verification, from test plan creation to sign-off.
Key Responsibilities
- Develop and implement UVM environments and testbenches
- Collaborate with domain specialists to drive core technical initiatives
- Work closely with cross-functional teams in globally dispersed locations
- Design and develop test plans, scoreboards, and code coverage analysis tools
- Pair with engineers to tackle complex high-speed PHY verification projects
Requirements
- 5+ years of experience in system-level design and verification
- Excellent knowledge of System Verilog, UVM methodology, debug, and VIP development
- Familiarity with SERDES, UNIPRO, PCIe, UFS, and DDR protocols
- Proven track record of building test plans, UVM environments, and testbenches
- Strong communication and teamwork skills
About the Opportunity
As a Verification Engineer at our organization, you will have the opportunity to work on cutting-edge projects and collaborate with a highly experienced team. Our company culture values diversity, innovation, and collaboration.
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