
Senior Design for Testability Specialist
2 weeks ago
In this key position, you will play a pivotal role in designing and implementing cutting-edge Digital Signal Processing architectures with a focus on Memory BIST for advanced System-on-Chip (SoC) designs.
- Key Responsibilities:
- Develop and implement DFT architecture with a strong emphasis on MBIST for SoC design;
- Integrate MBIST IPs, generate test insertion and verification infrastructure;
- Work on DFT planning, insertion, simulation, and pattern generation;
- Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle to ensure high coverage and test quality in scan and MBIST;
- Perform ATPG and MBIST pattern generation and debug failures from silicon bring-up.
Required Skills and Qualifications:
- Bachelor's or Master's degree in Electronics or a related field;
- A minimum of 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN, and MBIST;
- Proficiency in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent;
- Solid understanding of scan insertion, ATPG, boundary scan, and JTAG;
- Experience with memory test algorithms, repair analysis, and pattern generation;
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
Benefits:
- This is an exciting opportunity to work with cutting-edge technologies and collaborate with experienced professionals;
- Develop your skills in DFT and contribute to the creation of innovative SoC designs.
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