STA Lead

Senior Timing and Physical Design EngineerWe are seeking a seasoned Senior Timing and Physical Design Engineer to lead complex subsystems through robust timing closure and physical implementation.Develop and refine methodologies for Static Timing Analysis (STA) and Place and Route (PNR), tailored to the unique challenges of large, multi-interface, or...

We are seeking a Staff Design Engineer/Design Manager to lead our synthesis and static timing analysis efforts for an advanced mixed-signal chip.Job DescriptionThis role is responsible for developing and maintaining methodology and flows related to timing verification and closure, ensuring timely completion of projects.The ideal candidate will have thorough...

Job Description:As a Senior Physical Design Engineer, you will play a crucial role in the design and development of cutting-edge semiconductor products. The ideal candidate will have a strong background in physical design methodologies and experience with sub-micron technology nodes.Required Skills and Qualifications:Hands-on experience on Netlist2GDSII...

Key Responsibilities:Lead the planning and execution of all aspects of physical design, including floor planning, place and route, clock tree synthesis, clock distribution, extraction, timing closure, power and signal integrity analysis, physical verification, and DFM.Participate in all stages of the design process, from floor planning to routing and...

Lead Chip ArchitectWe are seeking a highly skilled and motivated Lead Chip Architect to oversee the overall chip architecture and design execution.Manage multi-block design integration and ensure seamless handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT.Drive IP integration, clocking strategy, and...

Company: Eteros Technologies India Private LimitedEteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad• Our world-wide customers are amongst The Who's...

We are seeking a skilled engineer to drive the development of digital test architecture, planning, and implementation across complex SoC/ASIC designs.The ideal candidate will have expertise in defining and driving DFT strategy and architecture for multiple ASIC/SoC projects, leading implementation and verification of DFT features like scan insertion and...